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INTEGRATED CIRCUITS
DATA SHEET
PCF2119x-2 LCD controllers/drivers
Product specification File under Integrated Circuits, IC12 28. August 2000
Philips Semiconductors
Product specification
LCD controllers/drivers
CONTENTS 1 1.1 2 3 4 5 6 6.1 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 FEATURES Note APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PAD INFORMATION Pad functions FUNCTIONAL DESCRIPTION LCD supply voltage generator Programming ranges LCD bias voltage generator Oscillator External clock Power-on reset Power-down mode Registers Busy flag Address Counter (AC) Display Data RAM (DDRAM) Character Generator ROM (CGROM) Character Generator RAM (CGRAM) Cursor control circuit Timing generator LCD row and column drivers Reset function INSTRUCTIONS Clear display Return home Entry mode set Display control (and partial power-down mode) Cursor or display shift Function set Set CGRAM address Set DDRAM address Read busy flag and read address Write data to CGRAM or DDRAM Read data from CGRAM or DDRAM 9 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.10 10 10.1 10.2 11 12 13 14 15 16 16.1 16.2 16.3 16.4 16.5 17 18 19 20
PCF2119x-2
EXTENDED FUNCTION SET INSTRUCTIONS AND FEATURES New instructions Icon control IM IB Normal/icon mode operation Screen configuration Display configuration TC1 and TC2 Set VLCD Reducing current consumption INTERFACES TO MPU Parallel interface I2C-bus interface LIMITING VALUES HANDLING DC CHARACTERISTICS AC CHARACTERISTICS TIMING CHARACTERISTICS APPLICATION INFORMATION General Application Information 8-bit operation, 1-line display using external reset 4-bit operation, 1-line display using external reset 8-bit operation, 2-line display I2C-bus operation, 1-line display BONDING PAD LOCATIONS DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
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Philips Semiconductors
Product specification
LCD controllers/drivers
1 FEATURES
PCF2119x-2
* Display supply voltage range, VLCD - VSS = 2.2 to 6.5 V * Direct mode to save current consumption for icon mode and Mux 1 : 9 (depending on VDD2 value and LCD liquid properties) * Very low current consumption (20 to 200 A): - Icon mode: <25 A - Power-down mode: <2 A. 1.1 Note
* Single-chip LCD controller/driver * 2-line display of up to 16 characters + 160 icons, or 1-line display of up to 32 characters + 160 icons * 5 x 7 character format plus cursor; 5 x 8 for kana (Japanese) and user defined symbols * Icon mode: reduced current consumption while displaying icons only * Icon blink function * On-chip: - Configurable 4 (3, 2) * voltage multiplier generating LCD supply voltage, independent of VDD, programmable by instruction (external supply also possible) - Temperature compensation of on-chip generated VLCD: -0.16 to -0.24 %/K (programmable by instruction) - Generation of intermediate LCD bias voltages - Oscillator requires no external components (external clock also possible). * Display Data RAM: 80 characters * Character Generator ROM: 240, 5 x 8 characters * Character Generator RAM: 16, 5 x 8 characters; 4 characters used to drive 160 icons, 8 characters used if icon blink feature is used in application * 4 or 8-bit parallel bus and 2-wire I2C-bus interface * CMOS compatible * 18 row and 80 column outputs * Multiplex rates 1 : 18 (for normal operation), 1 : 9 (for single line operation) and 1 : 2 (for icon only mode) * Uses common 11 code instruction set (extended) * Logic supply voltage range, VDD1 - VSS = 1.5 to 5.5 V (chip may be driven with two battery cells) * HVgen supply voltage range, VDD2,3 - VSS = 2.2 to 4.0V 4 ORDERING INFORMATION TYPE NUMBER PC2119RU/2 PC2119SU/2 PC2119VU/2
Icon mode is used to save current. When only icons are displayed, a much lower operating voltage VLCD can be used and the switching frequency of the LCD outputs is reduced. In most applications it is possible to use VDD as VLCD. 2 APPLICATIONS
* Telecom equipment * Portable instruments * Point-of-sale terminals. 3 GENERAL DESCRIPTION
The PCF2119x is a low power CMOS LCD controller and driver, designed to drive a dot matrix LCD display of 2-line by 16 or 1-line by 32 characters with 5 x 8 dot format. All necessary functions for the display are provided in a single chip, including on-chip generation of LCD bias voltages, resulting in a minimum of external components and lower system current consumption. The PCF2119x interfaces to most microcontrollers via a 4 or 8-bit bus or via the 2-wire I2C-bus. The chip contains a character generator and displays alphanumeric and kana (Japanese) characters. The letter `x' in PCF2119x characterizes the built-in character set. Various character sets can be manufactured on request.
PACKAGE NAME - - - chip with bumps in tray chip with bumps in tray chip with bumps in tray DESCRIPTION VERSION - - -
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Philips Semiconductors
Product specification
LCD controllers/drivers
5 BLOCK DIAGRAM
PCF2119x-2
handbook, full pagewidth
C1 to C80 118 to 127, 106 to 92 64...103 87 to 73, 71 to 57, 105...1444 52 to 38, 16 to 25 80
R17DUP 72 104
R1 to R18 27 to 34, 55...63 116 to 109, 145...153 26, 117 18 ROW DRIVERS 18 SHIFT REGISTER 18-BIT
VLCD1
12, 13 46...51
BIAS VOLTAGE GENERATOR
COLUMN DRIVERS 80 DATA LATCHES
VLCDSENSE
38
VLCD2
14, 15 39...45
VLCD GENERATOR
80 SHIFT REGISTER 5 x 12 BIT 5 OSCILLATOR CURSOR AND DATA CONTROL
172 144
OSC
VDD1 VDD1 2 VDD2 3 VSS1 VSS2
1...6
5
1, 2 7...14 3, 4 15...18
8, 9 22...29 10, 11 30...37
CHARACTER GENERATOR RAM (128 x 5) (CGRAM) 16 CHARACTERS 8
CHARACTER GENERATOR ROM (CGROM) 240 CHARACTERS
TIMING GENERATOR
T1 T2 T3
20 6
7 7 21 129 157
DISPLAY DATA RAM (DDRAM) 80 CHARACTERS/BYTES 7 ADDRESS COUNTER (AC) 7 7 INSTRUCTION DECODER 7 DISPLAY ADDRESS COUNTER
131
159
PD
DATA REGISTER (DR) 8 DB3/SA0 DB0/SA0
164 136
8 BUSY FLAG INSTRUCTION REGISTER 8 I/O BUFFER
PCF2119x
158 130
POR
137 to 139 DB1 to DB3
165...167
168...171 140 to 143
519 E
162 134
163 135
128 SCL
156
132, 133
MGK891
160...161
DB4 to DB7
R/W
RS
SDA
Fig.1 Block diagram.
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Philips Semiconductors
Product specification
LCD controllers/drivers
6 PAD INFORMATION
PCF2119x-2
The identification of each pad and its location is given in Chapter 18. 6.1 Pad functions Pad function description DESCRIPTION Logic supply voltage High voltage generator supply voltages (always put VDD2 = VDD3). This is the ground pad for all except the high voltage generator. This is the ground pad for the high voltage generator. This input is used for the generation of the LCD bias levels. This is the VLCD output pad if VLCD is generated internally. This pad must be connected to VLCD1. This input (VLCD) is used for the voltage multiplier's regulation circuitry. This pad must be connected to VLCD2. The data bus clock input is set HIGH to signal the start of a read or write operation; data is clocked in or out of the chip on the negative edge of the clock; note 1. These are three test pads. T1 and T2 must be connected to VSS1; T3 is left open-circuit and is not user accessible.
Table 1
SYMBOL VDD1 VDD2,3 VSS1 VSS2 VLCD1 VLCD2 VLCDSENSE E T1 T2 T3 R1 to R18; R17DUP C1 to C80 SCL POR PD SDA R/W RS
LCD row driver outputs R1 to R18; these pads output the row select waveforms to the display; R17 and R18 drive the icons. R17 has two pads R17 and R17DUP. LCD column driver outputs C1 to C80. I2C-bus serial clock input; note 1. External power-on reset input. PD selects the chip power-down mode; for normal operation PD = 0. I2C-bus serial data input/output; note 1. This is the read/write input. R/W selects either the read (R/W = 1) or write (R/W = 0) operation. This pad has an internal pull-up resistor. The RS input selects the register to be accessed for read and write. RS = 0, selects the instruction register for write and the busy flag and address counter for read. RS = 1, selects the data register for both read and write. This pad has an internal pull-up resistor. The 8-bit bidirectional data bus (3-state) transfers data between the system controller and the PCF2119x. DB7 may be used as the busy flag, signalling that internal operations are not yet completed. In 4-bit operations the 4 higher order lines DB7 to DB4 are used; DB3 to DB0 must be left open-circuit. Data bus line DB3 has an alternative function (SA0), when selected this is the I2C-bus address pad. Each data line has its own internal pull-up resistor; note 1. Oscillator or external clock input. When the on-chip oscillator is used this pad must be connected to VDD1.
DB0 to DB7
OSC Note
1. When the I2C-bus is used, the parallel interface pad E must be at logic 0. In the I2C-bus read mode DB0 - DB2 and DB3 - DB7 should be connected to VDD1 or left open-circuit. a) When the parallel bus is used, pads SCL and SDA must be connected to VSS1 or VDD1; they must not be left open-circuit. b) If the 4-bit interface is used without reading out from the PCF2119x (i.e. R/W is set permanently to logic 0), the unused ports DB0 to DB4 can either be set to VSS1 or VDD1 instead of leaving them open-circuit. 28. August 2000 5
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x-2
When VLCD is generated on-chip the VLCD pads should be decoupled to VSS with a suitable capacitor. The generated VLCD is independent of VDD and is temperature compensated. When the voltage generator and the direct mode are switched off, an external voltage may be supplied at connected pads VLCD1,2. VLCD1,2 may be higher or lower than VDD. During direct mode (program DM register bit) the internal voltage generator is turned off and the VLCD output voltage is directly connected to VDD2. This reduces the current consumption during icon mode and Mux 1 : 9 (depending on VDD2 value and LCD liquid properties). The LCD supply voltage generator ensures that, as long as VDD is in the valid range (2.2 to 4 V), the required peak voltage VOP = 6.5 V can be generated at any time. 7.3 LCD bias voltage generator
7 7.1
FUNCTIONAL DESCRIPTION LCD supply voltage generator
The LCD supply voltage may be generated on-chip. The voltage generator is controlled by two internal 6-bit registers: VA and VB. The nominal LCD operating voltage at room temperature is given by the relationship: V OP(nom) = ( integer value of register x 0.08 ) + 1.82 7.2 Programming ranges
Programmed value: 1 to 63. Voltage: 1.90 to 6.86 V. Tref = 27 C. Values producing more than 6.5 V at operating temperature are not allowed. Operation above this voltage may damage the device. When programming the operating voltage the VLCD temperature coefficient must be taken into account. Values below 2.2 V are below the specified operating range of the chip and are therefore not allowed. Value 0 for VA and VB switches the generator off (i.e. VA = 0 in character mode, VB = 0 in icon mode). Usually register VA is programmed with the voltage for character mode and register VB with the voltage for icon mode.
The intermediate bias voltages for the LCD display are also generated on-chip. This removes the need for an external resistive bias chain and significantly reduces the system current consumption. The optimum value of VLCD depends on the multiplex rate, the LCD threshold voltage (Vth) and the number of bias levels. Using a 5-level bias scheme for 1 : 18 maximum rate allows VLCD < 5 V for most LCD liquids. The intermediate bias levels for the different multiplex rates are shown in Table 2. These bias levels are automatically set to the given values when switching to the corresponding multiplex rate.
Table 2
Bias levels as a function of multiplex rate V1 Vop Vop Vop V2 3/4(1) 3/4 2/3 V3 1/2 1/2 2/3 V4 1/2 1/2 1/3 V5 1/4 1/4 1/3 V6 Vss Vss Vss
MULTIPLEX NUMBER RATE OF LEVELS 1 : 18 1:9 1:2 Note 5 5 4
1. The values in the above table are given relative to Vop - Vss, e.g. 3/4 means 3/4 x (Vop - Vss).
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Product specification
LCD controllers/drivers
7.4 Oscillator
PCF2119x-2
The instruction register can be written to but not read from by the system controller. The data register temporarily stores data to be read from the DDRAM and CGRAM. When reading, data from the DDRAM or CGRAM corresponding to the address in the instruction register is written to the data register prior to being read by the `read data' instruction. 7.9 Busy flag
The on-chip oscillator provides the clock signal for the display system. No external components are required and the OSC pad must be connected to VDD. 7.5 External clock
If an external clock is to be used this is input at the OSC pad. The resulting display frame frequency is given by: f OSC f frame = ------------3 072 Only in the power-down state is the clock allowed to be stopped (OSC connected to VSS), otherwise the LCD is frozen in a DC state. 7.6 Power-on reset
The busy flag indicates the internal status of the PCF2119x. A logic 1 indicates that the chip is busy and further instructions will not be accepted. The busy flag is output to pad DB7 when RS = 0 and R/W = 1. Instructions should only be written after checking that the busy flag is at logic 0 or waiting for the required number of cycles. 7.10 Address Counter (AC)
The PC2119x must be reset externally. This is an internal synchronous reset that requires 3 OSC cycles to be executed after release of the external reset signal. If no external reset is performed, the chip might start-up in an unwanted state. The external reset is active high. 7.7 Power-down mode
The address counter assigns addresses to the DDRAM and CGRAM for reading and writing and is set by the commands `set CGRAM address' and `set DDRAM address'. After a read/write operation the address counter is automatically incremented or decremented by 1. The address counter contents are output to the bus (DB6 to DB0) when RS = 0 and R/W = 1. 7.11 Display Data RAM (DDRAM)
The chip can be put into power-down mode by applying an external active high level to the PD pad. In power-down mode all static currents are switched off (no internal oscillator, no bias level generation and all LCD outputs are internally connected to VSS). During power-down, information in the RAMs and the chip state are preserved. Instruction execution during power-down is possible when pad OSC is externally clocked. 7.8 Registers
The DDRAM stores up to 80 characters of display data represented by 8-bit character codes. RAM locations which are not used for storing display data can be used as general purpose RAM. The basic RAM to display addressing scheme is shown in Fig.2. With no display shift the characters represented by the codes in the first 32 RAM locations starting at address 00H in line 1 are displayed. Figures 3 and 4 show the display mapping for right and left shift respectively. When data is written to or read from the DDRAM wrap-around occurs from the end of one line to the start of the next line. When the display is shifted each line wraps around within itself, independently of the others. Thus all lines are shifted and wrapped around together. The address ranges and wrap-around operations for the various modes are shown in Table 3.
The PCF2119x has two 8-bit registers, an Instruction Register (IR) and a Data Register (DR). The Register Select signal (RS) determines which register will be accessed. The instruction register stores instruction codes such as `display clear' and `cursor shift', and address information for the Display Data RAM (DDRAM) and Character Generator RAM (CGRAM).
Table 3
Address space and wrap-around operation MODE 1 x 32 00 to 4F 4F to 00 4F to 00 7 2 x 16 00 to 27; 40 to 67 27 to 40; 67 to 00 27 to 00; 67 to 40 1x9 00 to 27 27 to 00 27 to 00
Address space Read/write wrap-around (moves to next line) Display shift wrap-around (stays within line) 28. August 2000
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x-2
handbook, full pagewidth
display position DDRAM address
non-displayed DDRAM addresses 12345
00 01 02 03 04
30 31 32
1D 1E 1F 20 21 4C 4D 4E 4F
1-line display non-displayed DDRAM address 12345
00 01 02 03 04
14 15 16
0D 0E 0F 10 11 24 25 26 27
line 1
DDRAM address
12345
40 41 42 43 44
14 15 16
4D 4E 4F 50 51 64 65 66 67
MGK892
line 2
2-line display/MUX 1 : 9 mode
Fig.2 DDRAM to display mapping: no shift.
handbook, halfpage
1
23
4
5
14 15 16
0C 0D 0E
27 00 01 02 03
line 1
DDRAM address
1
23
4
5
10 11 12
4C 4D 4E
67 40 41 42 43
line 2
MGL536
2-line display/MUX 1 : 9 mode
Fig.3DDRAM to display mapping: right shift
display handbook, halfpage position DDRAM address 1 23 4 5 30 31 32
1E 1F 20 01 02 03 04 05
1-line display 1 DDRAM address 23 4 5 14 15 16
0E 0F 10
01 02 03 04 05
line 1
1
23
4
5
14 15 16
4E 4F 50
41 42 43 44 45
line 2
MGK894
2-line display/MUX 1 : 9 mode
Fig.4DDRAM to display mapping; left shift
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Philips Semiconductors
Product specification
LCD controllers/drivers
7.12 Character Generator ROM (CGROM) 7.15 Timing generator
PCF2119x-2
The Character Generator ROM generates 240 character patterns in a 5 x 8 dot format from 8-bit character codes. Figure 6 to 8 show the character sets that are currently implemented. 7.13 Character Generator RAM (CGRAM)
The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not disturbed by operations on the data buses. 7.16 LCD row and column drivers
Up to 16 user defined characters may be stored in the Character Generator RAM. Some CGRAM characters (see Fig.17) are also used to drive icons (6 if icons blink and both icon rows are used in the application; 3 if no blink but both icon rows are used in the application; 0 if no icons are driven by the icon rows). The CGROM and CGRAM use a common address space, of which the first column is reserved for the CGRAM (see Fig.6). Figure 9 shows the addressing principle for the CGRAM. 7.14 Cursor control circuit
The PCF2119x contains 18 row and 80 column drivers, which connect the appropriate LCD bias voltages in sequence to the display in accordance with the data to be displayed. R17 and R18 drive the icon rows. The bias voltages and the timing are selected automatically when the number of lines in the display is selected. Figures 10 to 13 show typical waveforms. Unused outputs should be left unconnected.
The cursor control circuit generates the cursor (underline and/or cursor blink as shown in Fig.5 at the DDRAM address contained in the address counter. When the address counter contains the CGRAM address the cursor will be inhibited.
cursor 5 x 7 dot character font alternating display
MGA801
cursor display example
blink display example
Fig.5 Cursor and blink display examples.
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Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x-2
handbook, full pagewidth upper
lower 4 bits xxxx
4 bits
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
MGL535
Fig.6 Character set `R' in CGROM.
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Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x-2
handbook, full pagewidth upper
lower 4 bits xxxx
4 bits
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
MGL534
Fig.7 Character set `S' in CGROM.
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Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x-2
handbook, full pagewidth upper
lower 4 bits xxxx
4 bits
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
MGL597
Fig.8 Character set `V' in CGROM.
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Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x-2
character handbook, full pagewidth codes (DDRAM data) 7 6 5 4 3 2 1 lower order bits 0 0 0 0 0 0 0 6 5
CGRAM address 4 3 2 1 lower order bits 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 higher order bits
character patterns (CGRAM data) 4 3 2 1 0 4
character code (CGRAM data) 3 2 1 0
higher order bits 0 0 0
higher order bits 0 0
lower order bits 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 character pattern example 2 0 0 0 0 character pattern example 1 cursor position 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 0 1 0 0 1 0 0 0 0 0 1 1 0 1 0 0 0 1 0 0 1 1 0 0 0 0 0 1 1 1 1 1 0 1 0 0 1 0 1 0 0 0 1 1 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 0 0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
MGE995
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
0 0 1 1
0 1 0 1
Character code bits 0 to 3 correspond to CGRAM address bits 3 to 6. CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position and display is performed by logical OR with the cursor. Data in the 8th position will appear in the cursor position. Character pattern column positions correspond to CGRAM data bits 0 to 4, as shown in Fig.6. As shown in Figs 6 and 7, CGRAM character patterns are selected when character code bits 4 to 7 are all logic 0. CGRAM data = logic 1 corresponds to selection for display. Only bits 0 to 5 of the CGRAM address are set by the `set CGRAM address' command. Bit 6 can be set using the `set DDRAM address' command in the valid address range or by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the `read busy flag and address counter' command.
Fig.9 Relationship between CGRAM addresses, data and display patterns.
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Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x-2
handbook, full pagewidth
frame n
frame n + 1
state 1 (ON) state 2 (OFF)
R1 R2 R3 R4 R5
ROW 1
VLCD V2 V3/V4 V5 VSS VLCD V2 V3/V4 V5 VSS VLCD V2 V3/V4 V5 VSS VLCD V2 V3/V4 V5 VSS VLCD V2 V3/V4 V5 VSS VOP
R6 R7 R8 R9
ROW 9
ROW 2
COL1
COL2
0.5VOP 0.25VOP state 1 0 V -0.25VOP -0.5VOP -VOP VOP 0.5VOP 0.25VOP state 2 0 V -0.25VOP -0.5VOP -VOP
MGE996
123
18 1 2 3
18
Fig.10 MUX 1 : 18 LCD waveforms; character mode.
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Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x-2
handbook, full pagewidth
frame n
frame n + 1
state 1 (ON) state 2 (OFF)
R1 R2 R3 R4 R5
ROW 1
VLCD V2 V3/V4 V5 VSS VLCD V2 V3/V4 V5 VSS VLCD V2 V3/V4 V5 VSS VLCD V2 V3/V4 V5 VSS VLCD V2 V3/V4 V5 VSS VOP
R6 R7 R8 R9
ROW 2
ROW 3
COL1
COL2
0.5VOP 0.25VOP state 1 0 V -0.25VOP -0.5VOP -VOP VOP 0.5VOP 0.25VOP state 2 0 V -0.25VOP -0.5VOP -VOP
1 9 1 9
MGK900
Fig.11 MUX 1 : 9 LCD waveforms; character mode. R10 to 18 to be left open.
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Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x-2
handbook, full pagewidth
frame n
frame n + 1 only icons are driven (MUX 1 : 2)
VLCD ROW 17 2/3 1/3 VSS
VLCD ROW 18 2/3 1/3 VSS
VLCD ROW 1 to 16 2/3 1/3 VSS
VLCD COL 1 ON/OFF 2/3 1/3 VSS
VLCD COL 2 OFF/ON 2/3 1/3 VSS
VLCD COL 3 ON/ON 2/3 1/3 VSS
VLCD COL 4 OFF/OFF 2/3 1/3 VSS
MGE997
Fig.12 MUX 1 : 2 LCD waveforms; icon mode.
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Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x-2
handbook, full pagewidth V PIXEL
frame n
frame n + 1 state 1 (ON)
state 1 COL 1 ROW 17
VOP 2/3 VOP 1/3 VOP 0 -1/3 VOP -2/3 VOP -VOP VOP 2/3 VOP 1/3 VOP 0 -1/3 VOP -2/3 VOP -VOP VOP 2/3 VOP 1/3 VOP
state 2 (OFF)
R17 R18 R1-16
state 3 (OFF)
state 2 COL 2 ROW 17
state 3 COL 1 0 ROW 1 to 16 -1/3 VOP -2/3 VOP -VOP
MGE998
VON(rms) = 0.745VOP VOFF(rms) = 0.333VOP V ON D = ------------- = 2.23 V OFF
Fig.13 MUX 1 : 2 LCD waveforms; icon mode.
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Product specification
LCD controllers/drivers
7.17 Reset function
PCF2119x-2
The PCF2119x must be reset externally when power is turned on. The reset executes a `clear display', requiring 165 oscillator cycles. After the reset the chip has the state shown in Table 4. Table 4 State after reset FUNCTION clear display entry mode set display control I/D = 1 S=0 3 D=0 C=0 B=0 4 function set DL = 1 M=0 H=0 SL = 0 5 +1 (increment) no shift display off cursor off cursor character blink off 8-bit interface 1-line display normal instruction set MUX 1 : 18 mode CONTROL BIT STATE CONDITION
STEP 1 2
default address pointer to DDRAM; the Busy Flag (BF) indicates the busy state (BF = 1) until initialization ends; the busy state lasts 2 ms; the chip may also be initialized by software; see Tables 18 and 19 icon control display/screen configuration VLCD temperature coefficient set VLCD I2C-bus interface reset Set HVgen stages IM, IB, DM = 000 L = 0; P = 0; Q = 0 TC1 = 0; TC2 = 0 icons, icon blink and direct mode disabled default configurations default temperature coefficient
6 7 8 9 10 11
VA = 0; VB = 0 (VLCD generator off)
S1, S0 = 10
HVgen set to 3 internal stages (4 * voltage multiplier)
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Philips Semiconductors
Product specification
LCD controllers/drivers
8 INSTRUCTIONS
PCF2119x-2
In normal use, category 3 instructions are used most frequently. However, automatic incrementing by 1 (or decrementing by 1) of internal RAM addresses after each data write lessens the MPU program load. The display shift in particular can be performed concurrently with display data write, enabling the designer to develop systems in minimum time with maximum programming efficiency. During internal operation, no instructions other than the `read busy flag' and `read address' instructions will be executed. Because the busy flag is set to a logic 1 while an instruction is being executed, check to ensure it is a logic 0 before sending the next instruction or wait for the maximum instruction execution time, as given in Table 6. An instruction sent while the busy flag is logic 1 will not be executed.
Only two PCF2119x registers, the Instruction Register (IR) and the Data Register (DR) can be directly controlled by the MPU. Before internal operation, control information is stored temporarily in these registers, to allow interfacing to various types of MPUs which operate at different speeds or to allow interface to peripheral control ICs. The PCF2119x operation is controlled by the instructions shown in Table 6 together with their execution time. Details are explained in subsequent sections. Instructions are of 4 types, those that: 1. Designate PCF2119x functions such as display format, data length, etc. 2. Set internal RAM addresses 3. Perform data transfer with internal RAM 4. Others. Table 5 Instruction set for I2C-bus commands CONTROL BYTE Co RS 0 Note 1. R/W is set together with the slave address. 0 0 0 0 0
COMMAND BYTE
I2C-BUS COMMANDS
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 note 1
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LCD controllers/drivers
INSTRUCTION H = 0 or 1 NOP Function set
RS
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DESCRIPTION
REQUIRED CLOCK CYCLES
0 0
0 0
0 0
0 0
0 1
0 DL
0 0
0 M
0 SL
0 H
no operation sets interface Data Length (DL) and number of display lines (M); single line/MUX 1 : 9 (SL), extended instruction set control (H) reads the Busy Flag (BF) indicating internal operating is being performed and reads address counter contents reads data from CGRAM or DDRAM writes data from CGRAM or DDRAM
3 3
Read busy flag and address counter Read data Write data H=0 Clear display Return home
0
1
BF
AC
0
1 1
1 0
read data write data
3 3
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 1
1 0
clears entire display and sets DDRAM address 0 in address counter sets DDRAM address 0 in address counter; also returns shifted display to original position; DDRAM contents remain unchanged sets cursor move direction and specifies shift of display; these operations are performed during data write and read sets entire display on/off (D), cursor on/off (C) and blink of cursor position character (B); D = 0 (display off) puts chip into the power-down mode moves cursor and shifts display without changing DDRAM contents sets CGRAM address; bit 6 is to be set by the command `set DDRAM address'; look at the description of the commands sets DDRAM address
165 3
Entry mode set
0
0
0
0
0
0
0
1
I/D
S
3
Display control
0
0
0
0
0
0
1
D
C
B
3
Cursor/display shift Set CGRAM address Set DDRAM address
0 0
0 0
0 0
0 1
0
1
S/C
R/L
0
0
3 3
ACG
PCF2119x-2
Product specification
0
0
1
ADD
3
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LCD controllers/drivers
INSTRUCTION H=1 Reserved Screen configuration Display configuration Icon control Temperature control Set HVgen stages Set VLCD Note 1. X = don't care.
RS
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DESCRIPTION
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 1
0 0 0 0 0 1 V
0 0 0 0 0 0
0 0 0 0 1 0
0 0 0 1 0 0
0 0 1 IM 0 0
0 1 P IB
1 L Q
do not use set screen configuration set display configuration
DM set icon mode (IM), icon blink (IB), direct mode(DM)
TC1 TC2 set temperature coefficient (TCx) S1 S0 set internal HVgen stages (S1,S0 = 11 not allowed) store VLCD in register VA or VB (V)
voltage
PCF2119x-2
Product specification
Philips Semiconductors
Product specification
LCD controllers/drivers
Table 7 Explanations of symbols used in Table 6
STATE BIT LOGIC 0 I/D S D C B S/C R/L DL H decrement display freeze display off cursor off cursor character blink off: character at cursor position does not blink cursor move left shift 4 bits use basic instruction set increment display shift display on cursor on
PCF2119x-2
LOGIC 1
cursor character blink on: character at cursor position blinks display shift right shift 8 bits use extended instruction set left/right screen: mirrored connection (as in PCF2116) 1st 16 characters of 32: columns are from 1 to 80 2nd 16 characters of 32: columns are from 80 to 1 column data: right to left; column data is displayed from 80 to 1 row data: bottom to top; row data is displayed from 16 to 1 and icon row data is in 18 and 17 icon mode; only icons displayed icon blink enabled direct mode enabled set VB 2-line by 16 display MUX 1 : 9 (1 x 16 character display) another control byte follows after data/command
L (no impact, if left/right screen: standard connection (as in M = 1 or SL = 1) PCF2114) 1st 16 characters of 32: columns are from 1 to 80 2nd 16 characters of 32: columns are from 1 to 80 P Q column data: left to right (as in PCF2116); column data is displayed from 1 to 80 row data: top to bottom (as in PCF2116); row data is displayed from 1 to 16 and icon row data is in 17 and 18 character mode; full display icon blink disabled direct mode disabled set VA 1-line by 32 display MUX 1 : 18 (1 x 32 or 2 x 16 character display) last control byte; see Table 5
IM IB DM V M (no impact, if SL = 1) SL C0
Table 8
TC1
Explanation of TC1 and TC2 used in Table 6
TC2 DESCRIPTION
0 1 0 1 Table 9
S1
0 0 1 1
VLCD temperature coefficient 0 VLCD temperature coefficient 1 VLCD temperature coefficient 2 VLCD temperature coefficient 3; for ranges for TC see Chapter 13
Explanation of S1 and S0 used in Table 6
S0 DESCRIPTION
0 0 1 1
0 1 0 1
set internal HVgen stages to 1 (2 * voltage multiplier) set internal HVgen stages to 2 (3 * voltage multiplier) set internal HVgen stages to 3 (4 * voltage multiplier) do not use
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22
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x-2
RS
R/W
E
DB7
IR7
IR3
BF
AC3
DR7
DR3
DB6
IR6
IR2
AC6
AC2
DR6
DR2
DB5
IR5
IR1
AC5
AC1
DR5
DR1
DB4
IR4 instruction write
IR0
AC4
AC0
DR4
DR0
busy flag and address counter read
data register read
MGA804
Fig.14 4-bit transfer example.
RS
R/W
E
internal
internal operation
DB7
IR7
IR3
busy
AC3
not busy
AC3
D7
D3
instruction write
busy flag check
busy flag check
instruction write
MGA805
IR7, IR3: instruction 7th, 3rd bit. AC3: address counter 3rd bit. D7, D3: data 7th, 3rd bit.
Fig.15 An example of 4-bit data transfer timing sequence.
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23
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x-2
RS
R/W
E
internal
internal operation
DB7
data instruction write
busy busy flag check
busy busy flag check
not busy busy flag check
data instruction write
MGA806
Fig.16 Example of busy flag checking timing sequence.
8.1
Clear display
8.3 8.3.1
Entry mode set I/D
`Clear display' writes character code 20H into all DDRAM addresses (the character pattern for character code 20H must be a blank pattern), sets the DDRAM address counter to logic 0 and returns the display to its original position, if it was shifted. Thus, the display disappears and the cursor or blink position goes to the left edge of the display. Sets entry mode I/D = 1 (increment mode). S of entry mode does not change. The instruction `clear display' requires extra execution time. This may be allowed by checking the Busy Flag (BF) or by waiting until the 165 clock cycles have elapsed. The latter must be applied where no read-back options are foreseen, as in some Chip-On-Glass (COG) applications. 8.2 Return home
When I/D = 1 (0) the DDRAM or CGRAM address increments (decrements) by 1 when data is written into or read from the DDRAM or CGRAM. The cursor or blink position moves to the right when incremented and to the left when decremented. The cursor underline and cursor character blink are inhibited when the CGRAM is accessed. 8.3.2 S
`Return home' sets the DDRAM address counter to logic 0 and returns the display to its original position if it was shifted. DDRAM contents do not change. The cursor or blink position goes to the left of the first display line. I/D and S of entry mode do not change.
When S = 1, the entire display shifts either to the right (I/D = 0) or to the left (I/D = 1) during a DDRAM write. Thus it appears as if the cursor stands still and the display moves. The display does not shift when reading from the DDRAM, or when writing to or reading from the CGRAM. When S = 0, the display does not shift.
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Philips Semiconductors
Product specification
LCD controllers/drivers
8.4 8.4.1 Display control (and partial power-down mode) D 8.5 Cursor or display shift
PCF2119x-2
The display is on when D = 1 and off when D = 0. Display data in the DDRAM is not affected and can be displayed immediately by setting D to a logic 1. When the display is off (D = 0) the chip is in partial power-down mode: * The LCD outputs are connected to VSS * The LCD generator and bias generator are turned off. Three oscillator cycles are required after sending the `display off' instruction to ensure all outputs are at VSS, afterwards OSC can be stopped. If the oscillator is running during partial power-down mode (`display off') the chip can still execute instructions. Even lower current consumption is obtained by inhibiting the oscillator (OSC = VSS). To ensure IDD <1 A, the parallel bus pads DB7 to DB0 should be connected to VDD; RS and R/W to VDD or left open-circuit and PD to VDD. Recovery from power-down mode: PD back to logic 0, if necessary OSC back to VDD and send a `display control' instruction with D = 1. 8.4.2 C
`Cursor/display shift' moves the cursor position or the display to the right or left without writing or reading display data. This function is used to correct a character or move the cursor through the display. In 2-line displays, the cursor moves to the next line when it passes the last position (40) of the line. When the displayed data is shifted repeatedly all lines shift at the same time; displayed characters do not shift into the next line. The Address Counter (AC) content does not change if the only action performed is shift display, but increments or decrements with the `cursor shift'. 8.6 8.6.1 Function set DL (PARALLEL MODE ONLY)
The cursor is displayed when C = 1 and inhibited when C = 0. Even if the cursor disappears, the display functions I/D, etc. remain in operation during display data write. The cursor is displayed using 5 dots in the 8th line (see Fig.5). 8.4.3 B
Sets interface data width. Data is sent or received in bytes (DB7 to DB0) when DL = 1 or in two nibbles (DB7 to DB4) when DL = 0. When 4-bit width is selected, data is transmitted in two cycles using the parallel bus. In a 4-bit application DB3 to DB0 should be left open-circuit (internal pull-ups). Hence in the first `function set' instruction after power-on M, SL and H are set to logic 1. A second `function set' must then be sent (2 nibbles) to set M, SL and H to their required values. `Function set' from the I2C-bus interface sets the DL bit to logic 1. 8.6.2 M
Selects either 1-line by 32 display (M = 0) or 2-line by 16 display (M = 1). 8.6.3 SL
The character indicated by the cursor blinks when B = 1. The cursor character blink is displayed by switching between display characters and all dots on with a period of f OSC approximately 1 second, with f blink = ---------------52 224 The cursor underline and the cursor character blink can be set to display simultaneously.
Selects MUX 1 : 9, 1-line by 16 display (independent of M and L). Only rows 1 to 8 and 17 are to be used. All other rows must be left open-circuit. The DDRAM map is the same as in the 2-line by 16 display mode, however, the second line is not displayable.
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Philips Semiconductors
Product specification
LCD controllers/drivers
8.6.4 H
PCF2119x-2
At the same time, the value of the address counter expressed in binary A6 to A0 is read out. The address counter is used by both CGRAM and DDRAM, and its value is determined by the previous instruction. 8.10 Write data to CGRAM or DDRAM
When H = 0 the chip can be programmed via the standard 11 instruction codes used in the PCF2116 and other LCD controllers. When H = 1 the extended range of instructions will be used. These are mainly for controlling the display configuration and the icons. 8.7 Set CGRAM address
`Write data' writes binary 8-bit data D7 to D0 to the CGRAM or the DDRAM. Whether the CGRAM or DDRAM is to be written into is determined by the previous `set CGRAM address' or `set DDRAM address' command. After writing, the address automatically increments or decrements by 1, in accordance with the entry mode. Only bits D4 to D0 of CGRAM data are valid, bits D7 to D5 are `don't care'. 8.11 Read data from CGRAM or DDRAM
`Set CGRAM address' sets bits 5 to 0 of the CGRAM address ACG into the address counter (binary A5 to A0). Data can then be written to or read from the CGRAM. Attention: the CGRAM address uses the same address register as the DDRAM address and consists of 7 bits (binary A6 to A0). With the `set CGRAM address' command, only bits 5 to 0 are set. Bit 6 can be set using the `set DDRAM address' command first, or by using the auto-increment feature during CGRAM write. All bits 6 to 0 can be read using the `read busy flag' and `read address' command. When writing to the lower part of the CGRAM, ensure that bit 6 of the address is not set (e.g. by an earlier DDRAM write or read action). 8.8 Set DDRAM address
`Read data' reads binary 8-bit data D7 to D0 from the CGRAM or DDRAM. The most recent `set address' command determines whether the CGRAM or DDRAM is to be read. The `read data' instruction gates the content of the Data Register (DR) to the bus while E is HIGH. After E goes LOW again, internal operation increments (or decrements) the AC and stores RAM data corresponding to the new AC into the DR. There are only three instructions that update the data register: * `set CGRAM address' * `set DDRAM address' * `read data' from CGRAM or DDRAM. Other instructions (e.g. `write data', `cursor/display shift', `clear display' and `return home') do not modify the data register content.
`Set DDRAM address' sets the DDRAM address ADD into the address counter (binary A6 to A0). Data can then be written to or read from the DDRAM. 8.9 Read busy flag and read address
`Read busy flag' and `read address' read the Busy Flag (BF) and Address Counter (AC). BF = 1 indicates that an internal operation is in progress. The next instruction will not be executed until BF = 0. It is recommended that the BF status is checked before the next write operation is executed.
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Philips Semiconductors
Product specification
LCD controllers/drivers
9 9.1 EXTENDED FUNCTION SET INSTRUCTIONS AND FEATURES New instructions 9.4 IB
PCF2119x-2
Icon blink control is independent of the cursor/character blink function. When IB = 0, icon blink is disabled. Icon data is stored in CGRAM character 0 to 3 (4 x 8 x 5 = 160 bits for 160 icons). When IB = 1, icon blink is enabled. In this case each icon is controlled by two bits. Blink consists of two half phases (corresponding to the cursor on and off phases called even and odd phases hereafter). Icon states for the even phase are stored in CGRAM characters 0 to 3 (4 x 8 x 5 = 160 bits for 160 icons). These bits also define icon state when icon blink is not used. Icon states for the odd phase are stored in CGRAM character 4 to 7 (another 160 bits for the 160 icons). When icon blink is disabled CGRAM characters 4 to 6 may be used as normal CGRAM characters.
H = 1, sets the chip into alternate instruction set mode. 9.2 Icon control
The PCF2119x can drive up to 160 icons. See Fig.17 for CGRAM to icon mapping. 9.3 IM
When IM = 0, the chip is in character mode. In the character mode characters and icons are driven (MUX 1 : 18). The VLCD generator, if used, produces the VLCD voltage programmed in register VA. When IM = 1, the chip is in icon mode. In the icon mode only the icons are driven (MUX 1 : 2) and the VLCD voltage generator, if used, produces the VLCD voltage as programmed in register VB. Table 10 Blink effect for icons and cursor character blink PARAMETER Cursor character blink Icons
EVEN PHASE block (all on) state 1: CGRAM character 0 to 2
ODD PHASE normal (display character) state 2: CGRAM character 4 to 6
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Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x-2
handbook, full pagewidth
display:
COL 1 to 5
COL 6 to 10
COL 76 to 80
ROW 17 -
1
2
3
4
5
6
7
8
9
10
76
77
78
79
80
ROW 18 -
81
82
83
84
85
86
87
88
89
90
156 157 158 159 160
MGL249
block of 5 columns
icon no. handbook, full pagewidth
phase
ROW/COL 7 MSB 6
character codes 5 4 3 2 1 0 LSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 MSB 0 0 0
CGRAM address 5 4 3 2 1 0 4
CGRAM data 3 2 1 0 LSB 0 1 1 1 0 1 0 1 1 1 0 0
icon view
LSB MSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0
1-5 6-10 11-15
even even even
17/1-5 17/6-10 17/11-15
0 0 0
76-80 81-85
even even
17/76-80 18/1-5
0 0
0 0
0 0
0 0
0 0
0 0
0 1
1 0
0 0
0 0
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 0
1 0
1 0
156-160 1-5
even odd (blink)
18/76-80 17/1-5
0 0
0 0
0 0
0 0
0 0
0 1
1 0
1 0
0 0
0 1
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
0 0
1 0
156-160
odd (blink)
18/76-80
0
0
0
0
0
1
1
1
0
1
1
1
1
1
1
0
0
1
1
0
MGK999
CGRAM data bit = logic 1 turns the icon on, data bit = logic 0 turns the icon off. Data in character codes 0 to 3 define the icon state when icon blink is disabled or during the even phase when icon blink is enabled. Data in character codes 4 to 7 define the icon state during the odd phase when icon blink is enabled (not used for icons when icon blink is disabled).
Fig.17 CGRAM to icon mapping.
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Philips Semiconductors
Product specification
LCD controllers/drivers
9.5 IM 0 1 9.6 Normal/icon mode operation CONDITION character mode icon mode Direct mode VLCD generates VA generates VB 9.10 TC1 and TC2
PCF2119x-2
Default is TC1 and TC2 = 0. This selects the default temperature coefficient for the internally generated VLCD. TC1 and TC2 = 10, 01 and 11 selects alternative temperature coefficients 1, 2 and 3 respectively. 9.11 Set VLCD
When DM = 0, the chip is not in direct mode. Either the internal voltage generator or an external voltage may be used to achieve the necessary VLCD value. When DM = 1, the chip is in direct mode. The internal voltage generator is turned off and the VLCD output is directly connected to the HVgen supply voltage VDD2. The direct mode can be used to reduce the current consumption when the required VLCD output voltage is close to the VDD2 supply voltage. This can be the case in icon mode or in Mux 1:9 (depending on LCD liquid properties). 9.7 S[1:0} A software configurable voltage multiplier is incorporated and can be set via the "Set HVgen stages" command. The voltage multiplier control can be used to reduce current consumption by disconnecting internal voltage multiplier stages (depending on the required VLCD output voltage). 9.8 Screen configuration Voltage multiplier control
The VLCD value is programmed by instruction. Two on-chip registers hold VLCD values for the character mode and the icon mode respectively (VA and VB). The generated VLCD value is independent of VDD, allowing battery operation of the chip. VLCD programming: 1. Send `function set' instruction with H = 1 2. Send `set VLCD' instruction to write to voltage register: a) DB7, DB6 = 10: DB5 to DB0 are VLCD of character mode (VA) b) DB7, DB6 = 11: DB5 to DB0 are VLCD of icon mode (VB) c) DB5 to DB0 = 000000 switches VLCD generator off (when selected) d) During `display off' and power-down the VLCD generator is also disabled. 3. Send `function set' instruction with H = 0 to resume normal programming. 9.12 Reducing current consumption
L: default is L = 0. L = 0: the two halves of a split screen are connected in a standard way i.e. column 1/81, 2/82 to 80/160. L = 1: the two halves of a split screen are connected in a mirrored way i.e. column 1/160, 2/159 to 80/81. This allows single layer PCB or glass layout. 9.9 Display configuration
Reducing current consumption can be achieved by one of the options given in Table 11. When VLCD lies outside the VDD range and must be generated, it is usually more efficient to use the on-chip generator than an external regulator. Table 11 Reducing current consumption ORIGINAL MODE Character mode Display on Any mode ALTERNATIVE MODE Icon mode (control bit IM) Display off (control bit D) Power-down (PD pad)
P, Q: default is P, Q = 0. P = 1: mirrors the column data. Q = 1: mirrors the row data.
HV generator operating Direct mode
Table 12 Use of the VA and VB registers MODE VA VB VLCD icon mode
Normal operation VLCD character mode
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Philips Semiconductors
Product specification
LCD controllers/drivers
10 INTERFACES TO MPU 10.1 Parallel interface
PCF2119x-2
The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. 10.2.1 I2C-BUS PROTOCOL
The PCF2119x can send data in either two 4-bit operations or one 8-bit operation and can thus interface to 4-bit or 8-bit microcontrollers. In 8-bit mode data is transferred as 8-bit bytes using the 8 data lines DB7 to DB0. Three further control lines E, RS and R/W are required; see Section 6.1. In 4-bit mode data is transferred in two cycles of 4 bits each using pads DB7 to DB4 for the transaction. The higher order bits (corresponding to DB7 to DB4 in 8-bit mode) are sent in the first cycle and the lower order bits (DB3 to DB0 in 8-bit mode) in the second. Data transfer is complete after two 4-bit data transfers. It should be noted that two cycles are also required for the busy flag check. 4-bit operation is selected by instruction, see Figs 14 to 16 for examples of bus protocol. In 4-bit mode, pads DB3 to DB0 must be left open-circuit. They are pulled up to VDD internally. 10.2 I2C-bus interface
Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always carried out with the first byte transmitted after the START procedure. The I2C-bus configuration for the different PCF2119x read and write cycles is shown in Figs 22 to 24. The slow down feature of the I2C-bus protocol (receiver holds SCL LOW during internal operations) is not used in the PCF2119x. 10.2.2 DEFINITIONS
The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are the Serial Data line (SDA) and the Serial Clock Line (SCL). Both lines must be connected to a positive supply via pull-up resistors. Data transfer may be initiated only when the bus is not busy. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter.
* Transmitter: the device which sends the data to the bus * Receiver: the device which receives the data from the bus * Master: the device which initiates a transfer, generates clock signals and terminates a transfer * Slave: the device addressed by a master * Multi-master: more than one master can attempt to control the bus at the same time without corrupting the message * Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted * Synchronization: procedure to synchronize the clock signals of two or more devices.
MASTER TRANSMITTER/ RECEIVER SDA SCL
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
MGA807
Fig.18 System configuration.
28. August 2000
30
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x-2
handbook, full pagewidth
SDA
SCL data line stable; data valid change of data allowed
MBC621
Fig.19 Bit transfer.
handbook, full pagewidth
SDA
SDA
SCL S START condition P STOP condition
SCL
MBC622
Fig.20 Definition of START and STOP conditions.
handbook, full pagewidth
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START condition clock pulse for acknowledgement
MBC602
1
2
8
9
Fig.21 Acknowledgement on the I2C-bus.
28. August 2000
31
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acknowledgement from PCF2119x S
Philips Semiconductors
handbook, full pagewidth
LCD controllers/drivers
S 0 1 1 1 0 1 A 0 A 1 RS CONTROL BYTE A
0 2n 0 bytes
DATA BYTE
A 0 RS CONTROL BYTE A
DATA BYTE
AP
slave address R/W Co
1 byte Co
n 0 bytes update data pointer
MGK899
32
S 011101A0 0 PCF2119x slave address R/W
PCF2119x-2
Product specification
Fig.22 Master transmits to slave receiver; write mode.
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th
28. August 2000
acknowledgement S
Philips Semiconductors
LCD controllers/drivers
S 0 1 1 1 0 1 A 0 A 1 RS CONTROL BYTE A
0
DATA BYTE
A 0 RS CONTROL BYTE A
DATA BYTE(1)
A
slave address R/W Co
2n
0 bytes Co
1 byte
n 0 bytes
acknowledgement
acknowledgement
no acknowledgement
S
SLAVE ADDRESS
S A1A 0
DATA BYTE
A
DATA BYTE
1P
33
n bytes R/W Co update data pointer
last byte update data pointer
MGG003
PCF2119x-2
Product specification
(1) Last data byte is a dummy byte (may be omitted).
Fig.23 Master reads after setting word address; writes word address, set RS; `read data'.
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x-2
dbook, full pagewidth
acknowledgement from PCF2113x
acknowledgement from master
no acknowledgement from master
S
SLAVE ADDRESS
S A1A 0
DATA BYTE
A
DATA BYTE
1P
n bytes R/W Co update data pointer
last byte update data pointer
MGG004
Fig.24 Master reads slave immediately after first byte; read mode (RS previously defined).
dbook, full pagewidth
SDA
t BUF
t LOW
tf
SCL
t HD;STA
tr
t HD;DAT
t HIGH
t SU;DAT
SDA t SU;STA
MGA728
t SU;STO
Fig.25 I2C-bus timing diagram.
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Philips Semiconductors
Product specification
LCD controllers/drivers
11 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD1 VDD2,3 VLCD VI(VDD) / VO(VDD) VI(VLCD) / VO(VLCD) II IO IDD, ISS and ILCD VHMB VMM Ptot PO Tstg 12 HANDLING Logic supply voltage High voltage generator supply voltages LCD supply voltage input/output voltage (any VDD related input/output) input/output voltage (any VLCD related input/output) DC input current DC output current VDD1,2,3, VSS1,2 or VLCD current electrostatic handling voltage according Human Body Model (C=100pF, R=1.5kOhm) electrostatic handling voltage according Machine Model(c=200pF, L=0.75uH) total power dissipation power dissipation per output storage temperature - - -65 PARAMETER MIN. -0.5 -0.5 -0.5 -0.5 -0.5 -10 -10 -50
PCF2119x-2
MAX. +6.5 +4.5 +7.5 VDD + 0.5 VLCD + 0.5 +10 +10 +50 1.8 150 400 100 +150 V V V V V mA mA mA kV V
UNIT
mW mW C
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see "Handling MOS Devices").
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Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x-2
13 DC CHARACTERISTICS VDD1 = 1.5 to 5.5 V; VDD2,3 = 2.2 to 4.0 V; VSS = 0 V; VLCD = 2.2 to 6.5 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL Supplies VDD1 VDD2,3 VLCD ISS ISS1 ISS3 ISS4 ISS5 Logic supply voltage High voltage generator supply voltages LCD supply voltage ground supply current ground supply current 1 ground supply current 3 ground supply current 4 ground supply current 5 VDD = 3 V; VLCD = 5 V; note 2 icon mode; VDD = 3 V; VLCD = 2.5 V; note 2 external VLCD; note 1 - - - 70 35 25 0.5 120 80 45 5 A A A A internal VLCD generation (VDD2,3 < VLCD) 1.5 2.2 2.2 - - - 5.5 4.0 6.5 V V V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
power-down mode; VDD = 3 V; - VLCD = 2.5 V; DB7 to DB0, RS and R/W = 1; OSC = 0; PD = 1 internal VLCD; note 1and 3 - VDD = 3 V; VLCD = 5 V; note 2 icon mode; VDD = 2.5 V; VLCD = 2.5 V; note 2 - -
ISS ISS6 ISS8 ISS9 Logic VIL VIH VIL(osc) VIH(osc) IOL(DB) IOH(DB) Ipu IL
ground supply current ground supply current 6 ground supply current 8 ground supply current 9
190 135 85
400 400 -
A A A
LOW-level input voltage HIGH-level input voltage LOW-level input voltage pad OSC HIGH-level voltage pad OSC LOW-level output current pads DB7 to DB0 HIGH-level output current pads DB7 to DB0 leakage current VDD = VDDmin, VDDmax VDD = VDDmin, VDDmax VOL = 0.4 V; VDD1 = 5 V VOH = 4 V; VDD1 = 5 V
VSS1 0.7VDD1 VSS1 VDD1 - 0.1 1.6 -1 0.04 -1
- - - - 4 -8 0.15 -
0.3VDD1 VDD1
V V
VDD1 - 1.2 V VDD1 - - 1 +1 V mA mA A A
pull-up current pads DB7 to DB0 VI = VSS1, VDDmin, VDDmax VI = VDD1,2,3 or VSS1,2
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Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x-2
SYMBOL I2C-bus SDA AND SCL VIL2 VIH2 ILI Ci IOL (SDA)
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
LOW-level input voltage HIGH-level input voltage input leakage current input capacitance low-level output current SDA VOL = 0.4 V ; VDD > 2V VOL = 0.2VDD ; VDD < 2V VI = VDD or VSS
0 0.7VDD -1 - 3 2 - - -
- - - 5
0.3VDD 5.5 +1 -
V V A pF mA mA
LCD outputs RO(ROW) RO(COL) Vbias(tol) VVLCD(tol) row output resistance pads R1 to R18 column output resistance pads C1 to C80 bias tolerance pads R1 to R18 and C1 to C80 VLCD tolerance note 4 note 4 note 5 Tamb = 25 C; note 3 VLCD < 3 V VLCD < 4 V VLCD < 5 V VLCD < 6 V TC0 TC1 TC2 TC3 Notes 1. LCD outputs are open-circuit; inputs at VDD or VSS; bus inactive. 2. Tamb = 25 C; fOSC = 200 kHz. 3. LCD outputs are open-circuit; HV generator is on; load current IVLCD (at VLCD) = 5 A. 4. Resistance of output terminals (R1 to R18 and C1 to C80) with a load current of 10 A; outputs measured one at a time; external VLCD ; VLCD = 3 V, VDD1,2,3 = 3 V. 5. LCD outputs open-circuit; external VLCD. VLCD temperature coefficient 0 VLCD temperature coefficient 1 VLCD temperature coefficient 2 VLCD temperature coefficient 3 - - - - - - - - - - - - -0.16 -0.18 -0.21 -0.24 160 200 260 340 - - - - mV mV mV mV %/K %/K %/K %/K 10 15 20 30 40 130 k k mV
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Philips Semiconductors
Product specification
LCD controllers/drivers
14 AC CHARACTERISTICS
PCF2119x-2
VDD1 = 1.5 to 5.5 V; VDD2,3 = 2.2 to 4.0 V; VSS = 0 V; VLCD = 2.2 to 6.5 V; Tamb = -40 to +85 C; unless otherwise specified.
SYMBOL
fFR fOSC fOSC(ext) tOSCST tW(R,PD) tSW(R,PD)
PARAMETER
LCD frame frequency (internal clock) oscillator frequency (not available at any pad) external clock frequency oscillator start-up time after power-down reset and power down high level pulse width tolerable spike width on PD and Reset pads
CONDITIONS
VDD = 5.0 V 45 140 140 note 3 - 1
MIN.
TYP.
95 250 - 200
MAX.
147 450 450 300 90
UNIT
Hz kHz kHz s us ns
Bus timing characteristics: parallel interface; note 1 WRITE OPERATION (WRITING DATA FROM MPU TO PCF2119X) Tcy(en) tW(en) tsu(A) th(A) tsu(D) th(D) enable cycle time enable pulse width address set-up time address hold time data set-up time data hold time 500 220 50 25 60 25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 150 250 100 ns ns ns ns ns ns
READ OPERATION (READING DATA FROM PCF2119X TO MPU) Tcy(en) tW(en) tsu(A) th(A) td(D) th(D) enable cycle time enable pulse width address set-up time address hold time data delay time data hold time I2C-bus interface; note 1 - 1.3 0.6 100 0 400 - - - - 300 300 400 - - - 50 kHz s s ns ns ns ns pF s s s ns us VDD1 > 2.2 V VDD1 > 1.5 V 500 220 50 25 - - 5 ns ns ns ns ns ns ns
Timing characteristics: fSCL tLOW tHIGH tSU;DAT tHD;DAT tr tf CB tSU;STA tHD;STA tSU;STO tSW tBUF
SCL clock frequency SCL clock low period SCL clock high period data set-up time data hold time SCL, SDA rise time SCL, SDA fall time capacitive bus line load set-up time for a repeated START condition START condition hold time set-up time for STOP condition tolerable spike width on bus
Bus free time between STOP and START condition
note 2, 3
note 2, 3
15 + 0.1 CB 15 + 0.1 CB - 0.6 0.6 0.6 - 1.3
Note
1. 2. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. CB = total capacitance of one bus line in pF. Tested on a sample basis.
3.
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Philips Semiconductors
Product specification
LCD controllers/drivers
15 TIMING CHARACTERISTICS
PCF2119x-2
handbook, full pagewidth
RS
VIH1 V IL1 t su(A)
VIH1 VIL1 t h(A)
R/W
V IL1 tW(en)
VIL1 t h(A) VIL1 t h(D) VIH1 VIL1
MBK474
E
VIH1 VIL1
VIH1 VIL1 t su(D) VIH1 valid data VIL1 Tcy(en)
DB0 to DB7
Fig.26 Parallel bus write operation sequence; writing data from MPU to PCF2119x.
handbook, full pagewidth
RS
VIH1 V IL1 tsu(A)
VIH1 VIL1 t h(A) VIH1
R/W
VIH1
tW(en) E VIL1 VIH1 VIH1
t h(A) VIL1 VIL1
t d(D) DB0 to DB7 VOH1 VOL1 Tcy(en)
t h(D) VOH1 VOL1
MBK475
Fig.27 Parallel bus read operation sequence; reading data from PCF2119x to MPU.
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Philips Semiconductors
Product specification
LCD controllers/drivers
16 APPLICATION INFORMATION 16.1 General application information
PCF2119x-2
The required minimum value for the external capacitors in an application with the PCF2119x-2 are: Cext for VLCD/VSS1,2 = min. 100nF, for VDD1,2,3 / VSS1,2 = 470nF. Higher capacitor values are recommended for ripple reduction. For COG applications the recommended ITO track resistance is to be minimized for the I/O and supply connections. Optimized values for these tracks are below 50 Ohm for the supply and below 100 Ohm for the I/O connections. Higher track resistance reduces performance and increase current consumption. To avoid accidental triggering of power-on reset (especially in COG applications), the supplies must be adequately decoupled. Depending on power supply quality, VDD1 may have to be rised above the specified minimum.
handbook, full pagewidth
P20 P21 P80CL51 P22
RS R/W E
R17, R18
2
R1 to R16 PCF2119x 16
2 x 16 CHARACTER LCD DISPLAY PLUS 160 ICONS 80
MGK895
P17 to P10
8
DB7 to DB0
C1 to C80
Fig.28 Direct connection to 8-bit MPU; 8-bit bus.
handbook, full pagewidth
P10 P11 P80CL51 P12
RS R/W E
R17, R18
2
R1 to R16 PCF2119x 16
2 x 16 CHARACTER LCD DISPLAY PLUS 160 ICONS 80
MGK896
P17 to P14
4
DB7 to DB4
C1 to C80
Fig.29 Direct connection to 8-bit MPU; 4-bit bus.
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Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x-2
handbook, full pagewidth
OSC VDD
R17, R18
2
VDD R1 to R16 PCF2119x 100 nF VLCD 100 nF VSS C1 to C80 16
2 x 16 CHARACTER LCD DISPLAY PLUS 160 ICONS 80
VSS
8 DB7 to DB0 E RS R/W
MGK897
Fig.30 Typical application using parallel interface.
handbook, full pagewidth
VDD VDD
VDD
OSC VDD
DB3/SAO
R17, R18
2
VDD R1 to R16 PCF2119x 16
100 nF VSS
VLCD 100 nF VSS SCL SDA C1 to C80
2 x 16 CHARACTER LCD DISPLAY PLUS 160 ICONS 80
VSS
OSC VDD
DB3/SAO
R17, R18
2
VDD R1 to R16 PCF2119x 16
100 nF VSS
VLCD 100 nF VSS SCL SDA C1 to C80
1 x 32 CHARACTER LCD DISPLAY PLUS 160 ICONS 80
SCL SDA
MASTER TRANSMITTER PCF84C81A; P80CL410
MGK898
Fig.31 Application using I2C-bus interface.
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Philips Semiconductors
Product specification
LCD controllers/drivers
16.2 Charge pump characteristic
PCF2119x-2
In Fig. 32 - 34 typical graphs of the total power consumption of the PCF2119-2 using the internal charge pump are given. They are obtained under the following conditions : * ambient temperature 25C * VDD1 = VDD2 = VDD3 = 2.2 (min), 2.7 (typ), 4V (max) * normal mode * Fosc = internal oscillator * MUX 1:18 * typical load current IVLCD = 10 uA For each multiplication factor there is a separate line. A line ends where it is not possible to get a higher voltage under its conditions (a higher multiplication factor is needed to get higher voltages). Connecting different displays may result in different current consumptions. This affects the efficiency and the optimal multiplication factor to be used to generate a certain output voltage.
2x 3x 4x
2.75
3.5
4.25 Vop [V]
5
5.75
6.5
Fig.32 Typical charge pump characteristic for VDD = 2.2 V.
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42
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x-2
2x 3x 4x
2.75
3.5
4.25 Vop [V]
5
5.75
6.5
Fig.33 Typical charge pump characteristic for VDD = 2.7 V.
2x 3x 4x
2.75
3.5
4.25 Vop [V]
5
5.75
6.5
Fig.34 Typical charge pump characteristic for VDD = 4 V.
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Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x-2
functions (see Table 13 step 3). Thus, DB4 to DB7 of the `function set' are written twice. 16.5 8-bit operation, 2-line display
16.3
8-bit operation, 1-line display using external reset
Table 14 shows an example of a 1-line display in 8-bit operation. The PCF2119x functions must be set by the `function set' instruction prior to display. Since the DDRAM can store data for 80 characters, the RAM can be used for advertising displays when combined with display shift operation. Since the display shift operation changes display position only and the DDRAM contents remain unchanged, display data entered first can be displayed when the `return home' operation is performed. 16.4 4-bit operation, 1-line display using external reset
For a 2-line display, the cursor automatically moves from the first to the second line after the 40th digit of the first line has been written. Thus, if there are only 8 characters in the first line, the DDRAM address must be set after the 8th character is completed (see Table 6). It should be noted that both lines of the display are always shifted together; data does not shift from one line to the other. 16.6 I2C-bus operation, 1-line display
A control byte is required with most commands (see Table 17).
The program must set functions prior to a 4-bit operation, see Table 13. When power is turned on, 8-bit operation is automatically selected and the PCF2119x attempts to perform the first write as an 8-bit operation. Since nothing is connected to DB0 to DB3, a rewrite is then required. However, since one operation is completed in two accesses of 4-bit operation, a rewrite is required to set the
Table 13 4-bit operation, 1-line display example; using external reset STEP 1 2 INSTRUCTION power supply on (PCF2119x is initialized by the external reset) function set RS 0 3 R/W 0 DB7 0 DB6 0 DB5 1 DB4 0 sets to 4-bit operation; in this instance operation is handled as 8-bits by initialization and only this instruction completes with one write sets to 4-bit operation, selects 1-line display and VLCD = V0; 4-bit operation starts from this point and resetting is needed _ turns on display and cursor; entire display is blank after initialization DISPLAY OPERATION initialized; no display appears
function set 0 0 0 0 0 0 0 0 1 0 0 0
4
display on/off control 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 0 0 0 _
5
entry mode set 0 0 sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the DD/CGRAM; display is not shifted writes `P'; the DDRAM has already been selected by initialization at power-on; the cursor is incremented by 1 and shifted to the right
6
`write data' to CGRAM/DDRAM 1 1 0 0 0 0 1 0 0 0 1 0 P_
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44
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 28. August 2000 45 6 7 to 11 `write data' to CGRAM/DDRAM 1 0 0 1 0 0 1 0 0 0 PH_ | | 12 13 14 15 16 `write data' to CGRAM/DDRAM 1 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 1 1 0 0 1 1 0 1 PHILIPS_ PHILIPS_ HILIPS _ ILIPS | | | M_ writes `S' sets mode for display shift at the time of write writes space entry mode set `write data' to CGRAM/DDRAM `write data' to CGRAM/DDRAM writes `M' writes `H' Philips Semiconductors Table 14 8-bit operation, 1-line display example; using external reset (character set `A')
LCD controllers/drivers
STEP 1 2
INSTRUCTION power supply on (PCF2119x is initialized by the external reset) function set RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 1 0 0 _
DISPLAY
OPERATION initialized; no display appears
sets to 8-bit operation, selects 1-line display and VLCD = V0 turns on display and cursor; entire display is blank after initialization sets mode to increment the address by 1 and to shift the cursor to the right at the time of the write to the DD/CGRAM; display is not shifted writes `P'; the DDRAM has already been selected by initialization at power-on; the cursor is incremented by 1 and shifted to the right
3
display mode on/off control 0
4
entry mode set 0 0 0 0 0 0 0 1 1 0 _
5
`write data' to CGRAM/DDRAM 1 0 0 1 0 1 0 0 0 0 P_
PCF2119x-2
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 28. August 2000 46 25 return home 0 0 0 0 0 0 0 0 1 0 PHILIPS M returns both display and cursor to the original position (address 0) Philips Semiconductors STEP 17 18 19 20 21 22 23 24 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 INSTRUCTION `write data' to CGRAM/DDRAM 0 0 0 0 0 0 0 0 1 1 0 1 1 0 1 0 0 0 1 0 1 1 0 0 0 1 1 1 1 0 0 1 0 0 0 1 0 0 1 0 0 1 MICROKO MICROKO MICROKO ICROCO MICROCO MICROCO_ ICROCOM_ | | | writes `O' shifts only the cursor position to the left shifts only the cursor position to the left writes `C' correction; the display moves to the left shifts the display and cursor to the right shifts only the cursor to the right writes `M' cursor/display shift cursor/display shift `write data' to CGRAM/DDRAM cursor/display shift cursor/display shift `write data' to CGRAM/DDRAM DISPLAY OPERATION
LCD controllers/drivers PCF2119x-2
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 28. August 2000 47 Philips Semiconductors Table 15 8-bit operation, 1-line display and icon example; using external reset (character set `A')
LCD controllers/drivers
STEP 1 2
INTRODUCTION power supply on (PCF2119x is initialized by the external reset) function set RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 1 0 0 _
DISPLAY
OPERATION initialized; no display appears
sets to 8-bit operation, selects 1-line display and VLCD = V0 turns on display and cursor; entire display is blank after initialization sets mode to increment the address by 1 and to shift the cursor to the right at the time of the write to the DD/CGRAM; display is not shifted sets the CGRAM address to position of character 0; the CGRAM is selected writes data to CGRAM for icon even phase; icons appears | |
3
display mode on/off control 0
4
entry mode set 0 0 0 0 0 0 0 1 1 0 _
5
set CGRAM address 0 0 0 1 0 0 0 0 0 0 _
6 7
`write data' to CGRAM/DDRAM 1 0 0 0 0 0 1 0 1 0 _
8
set CGRAM address 0 0 0 1 1 1 0 0 0 0 _ sets the CGRAM address to position of character 4; the CGRAM is selected writes data to CGRAM for icon odd phase | |
9 10
`write data' to CGRAM/DDRAM 1 0 0 0 0 0 1 0 1 0 _
PCF2119x-2
11 12 13
function set 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 0 0 0 0 0 1 0 1 0 1 _ _ _ sets H = 1 icons blink sets H = 0 icon control function set
Product specification
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LCD controllers/drivers
`write data' to CGRAM/DDRAM 1 0 0 1 0 1 0 0 0 0
16 17 to 20
`write data' to CGRAM/DDRAM 1 0 0 1 0 0 1 0 0 0 PH_
PCF2119x-2
Product specification
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LCD controllers/drivers
STEP 1 2
INTRODUCTION power supply on (PCF2119x is initialized by the external reset) function set RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 1 0 0 _
DISPLAY
OPERATION initialized; no display appears
sets to 8-bit operation; selects 2-line display and voltage generator off
3
display on/off control 0 turns on display and cursor; entire display is blank after initialization sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the CG/DDRAM; display is not shifted writes `P'; the DDRAM has already been selected by initialization at power-on; the cursor is incremented by 1 and shifted to the right
4
entry mode set 0 0 0 0 0 0 0 1 1 0 _
5
`write data' to CGRAM/DDRAM 1 0 0 1 0 1 0 0 0 0 P_
PCF2119x-2
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 28. August 2000 50 Philips Semiconductors STEP 20 1 21 0 0 1 INTRODUCTION `write data' to CGRAM/DDRAM 0 0 1 1 1 1 PHILIPS MICROCO_ PHILIPS MICROCO_ HILIPS ICROCOM_ | | | 24 return home 0 0 0 0 0 0 0 0 1 0 PHILIPS MICROCOM returns both display and cursor to the original position (address 0) writes `O' DISPLAY OPERATION
LCD controllers/drivers
`write data' to CGRAM/DDRAM 0 0 0 0 0 0 0 1 1 1 sets mode for display shift at the time of write
22
`write data' to CGRAM/DDRAM 1 0 0 1 0 0 1 1 0 1 writes `M'; display is shifted to the left; the first and second lines shift together
23
PCF2119x-2
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 28. August 2000 51 7 8 9 10 11 Philips Semiconductors Table 17 Example of I2C-bus operation; 1-line display (using external reset, assuming SA0 = VSS; note 1) STEP 1 2 I2C-bus start I2C BYTE slave address for write SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack 0 3 Co 0 4 1 RS 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 Ack 1 selects 1-line display and VLCD = V0; SCL pulse during acknowledge cycle starts execution of instruction send a control byte for `function set' control byte sets RS for following data bytes during the acknowledge cycle SDA will be pulled-down by the PCF2119x DISPLAY OPERATION initialized; no display appears
LCD controllers/drivers
function set DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 0 1 X 0 0 0 0 1 _
5
display on/off control DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 0 0 0 1 1 1 0 1 _ turns on display and cursor; entire display shows character 20H (blank in ASCII-like character sets)
6
entry mode set DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 0 0 0 0 1 1 0 1 _ sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the DDRAM or CGRAM; display is not shifted for writing data to DDRAM, RS must be set to 1; therefore a control byte is needed
I2C start slave address for write SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack 0 Co 0 1 RS 1 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 Ack 1 send a control byte for `write data'
_
_
`write data' to DDRAM
PCF2119x-2
Product specification
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 1 0 0 0 0 1 `write data' to DDRAM DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 0 1 0 0 0 1
P_
writes `P'; the DDRAM has been selected at power-up; the cursor is incremented by 1 and shifted to the right
PH_
writes `H'
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 28. August 2000 52 20 21 22 23 Philips Semiconductors STEP 12 to 15 I2C BYTE DISPLAY | | | | 16 `write data' to DDRAM DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 17 18 1 0 1 0 0 1 1 1 PHILIPS_ (optional I2C stop) I2C start + slave address for write (as step 8) control byte Co 1 19 RS 0 0 0 0 0 0 0 0 0 0 0 0 0 Ack 1 PHILIPS sets DDRAM address 0 in address counter (also returns shifted display to original position; DDRAM contents unchanged); this instruction does not update the Data Register (DR) PHILIPS_ PHILIPS_ writes `S' OPERATION
LCD controllers/drivers
return home DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 0 0 0 0 0 1 0 1 PHILIPS PHILIPS during the acknowledge cycle the content of the DR is loaded into the internal I2C-bus interface to be shifted out; in the previous instruction neither a `set address' nor a `read data' has been performed; therefore the content of the DR was unknown; the R/W has to be set to 1 while still in I2C-write mode DDRAM content will be read from following instructions
I2C start slave address for read SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack 0 1 1 1 0 1 0 1 1
control byte for read Co 0 RS 1 0 1 0 0 0 0 0 0 0 0 0 0 Ack 1 PHILIPS 8 x SCL; content loaded into interface during previous acknowledge cycle is shifted out over SDA; MSB is DB7; during master acknowledge content of DDRAM address 01 is loaded into the I2C-bus interface PHILIPS
`read data': 8 x SCL + master acknowledge; note 2
PCF2119x-2
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack X X X X X X X X 0
Product specification
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LCD controllers/drivers
26 Notes
I2C stop
PHILIPS
1. X = don't care. 2. SDA is left at high-impedance by the microcontroller during the read acknowledge.
PCF2119x-2
Product specification
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LCD controllers/drivers
STEP power-on or unknown state | wait 2 ms after external reset has been applied | RS 0 R/W 0 DB7 0 DB6 0 DB5 1 | wait 2 ms | RS 0 R/W 0 DB7 0 DB6 0 DB5 1 | wait more than 40 s | RS 0 R/W 0 DB7 0 DB6 0 DB5 1 | | RS 0 0 0 0 R/W 0 0 0 0 DB7 0 0 0 0 DB6 0 0 0 0 DB5 1 0 0 0 | Initialization ends Note 1. X = don't care. DB4 1 0 0 0 DB3 0 1 0 0 DB2 M 0 0 1 DB1 0 0 0 I/D DB0 H 0 1 S display off clear display entry mode set DB4 1 DB3 X DB2 X DB1 X DB0 X DB4 1 DB3 X DB2 X DB1 X DB0 X DB4 1 DB3 X DB2 X DB1 X DB0 X
DESCRIPTION
BF cannot be checked before this instruction function set (interface is 8 bits long)
BF cannot be checked before this instruction function set (interface is 8 bits long)
BF cannot be checked before this instruction function set (interface is 8 bits long) BF can be checked after the following instructions; when BF is not checked, the waiting time between instructions is the specified instruction time (see Table 3) function set (interface is 8 bits long); specify the number of display lines
PCF2119x-2
Product specification
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LCD controllers/drivers
STEP power-on or unknown state | Wait 2 ms after external reset has been applied | RS 0 Wait 2 ms | RS 0 Wait 40 s | RS 0 R/W 0 DB7 0 | RS 0 0 0 0 0 0 0 0 0 R/W 0 0 0 0 0 0 0 0 0 DB7 0 0 0 0 1 0 0 0 0 | Initialization ends DB6 0 0 M 0 0 0 0 0 1 DB5 1 1 0 0 0 0 0 0 I/D DB4 0 0 H 0 0 0 1 0 S entry mode set display off clear display DB6 0 DB5 1 DB4 1 R/W 0 DB7 0 | DB6 0 DB5 1 DB4 1 R/W 0 DB7 0 | DB6 0 DB5 1 DB4 1
DESCRIPTION
BF cannot be checked before this instruction function set (interface is 8 bits long)
BF cannot be checked before this instruction function set (interface is 8 bits long)
BF cannot be checked before this instruction function set (interface is 8 bits long) BF can be checked after the following instructions; when BF is not checked, the waiting time between instructions is the specified instruction time (see Table 3) function set (set interface to 4 bits long) interface is 8 bits long function set (interface is 4 bits long) specify number of display lines
PCF2119x-2
Product specification
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x-2
17 DEVICE PROTECTION DIAGRAM
VSS2-SUPPLY
VSS2
VDD2-SUPPLY
VDD2
VDD3-SUPPLY
VDD3
VSS1 VSS1
VDD1-SUPPLY
VDD1 VSS2
VSS2-SUPPLY
VSS1
VSS1-SUPPLY
PROTECTION OF LV SUPPLIES
LCD-O/'P'S
VLCDSENSE, VLCD2, VLCD1 VLCDIN
VSS1 VSS1
PROTECTION OF HV SUPPLIES AND I/O'S
I2C PADS
VDD1
CONTROL-PINS
VDD1
E, T1, T2, T3, POR, PD RW, RS, DB0-DB7, OSC VSS1 VSS1
PROTECTION OF I/O'S
Fig.35 ESD protection diagram 28. August 2000 56
Philips Semiconductors
Product specification
LCD controllers/drivers
18 BONDING PAD LOCATIONS
PCF2119x-2
dummy (Vss1) ROW8 ROW7 ROW6 ROW5 ROW4 ROW3 ROW2 ROW1 ROW17 COL80 COL79 COL78 COL77 COL76 COL75 COL74 COL73 COL72 COL71 COL70 COL69 COL68 COL67 COL66 COL65 COL64 COL63 COL62 COL61 COL60 COL59 COL58 COL57 COL56 COL55 COL54 COL53 COL52 COL51 COL50 COL49 COL48 COL47 COL46 COL45 COL44 COL43 COL42 COL41 ROW17 Repeated COL40 COL39 COL38 COL37 COL36 COL35 COL34 COL33 COL32 COL31 COL30 COL29 COL28 COL27 COL26 COL25 COL24 COL23 COL22 COL21 COL20 COL19 COL18 COL17 COL16 COL15 COL14 COL13 COL12 COL11 COL10 COL9 COL8 COL7 COL6 COL5 COL4 COL3 COL2 COL1 ROW18 ROW9 ROW10 ROW11 ROW12 ROW13 ROW14 ROW15 ROW16 dummy (Vss1)
50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150
49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 168 167 166 165 164 163 162 161 160 159 158
VLCDin VLCDin VLCDin VLCDin VLCDin VLCDin VLCDout VLCDout VLCDout VLCDout VLCDout VLCDout VLCDout VLCDsense VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1
T2 T1
Y X
E VDD3 VDD3 VDD3 VDD3 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 OSC DB7
PC2119-2
DB6 DB5 DB4
DB3 DB2
DB1 DB0 RS RW SDA SDA
PC2119-2
157 156
155 154 153 152 151
PD POR T3 SCL SCL
Chip size : 1.81 mm x 7.64 mm
Fig.36 Bonding pad locations.
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57
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x-2
handbook, full pagewidth
x
A
y
1,1 1,2 1,3
2,1 2,2
3,1
x,1
D B
F
1,y
x,y
E
MGR977
Fig.37 Tray details.
Table 20 Dimensions for Fig.37 DIM.
handbook, halfpage
DESCRIPTION pocket pitch, x direction pocket pitch, y direction pocket width, x direction pocket width, y direction tray width, x direction tray width, y direction number of pockets in x direction number of pockets in y direction
VALUE 10.16 mm 4.45 mm 7.74 mm 1.91 mm 50.8 mm 50.8 mm 4 10
A B C D E
PCF2119-1
F x y
PC2119-2
MGR978
The orientation of the IC in a pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Refer to the bonding pad location diagram for the orientating and position of the type name on the die surface.
Fig.38 Tray alignment.
28. August 2000
58
Philips Semiconductors
Product specification
LCD controllers/drivers
Table 21 Bonding pad locations Dimensions in m; all x/y coordinates are referenced to centre of chip; see Fig.36
SYMBOL VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD3 VDD3 VDD3 VDD3 E T1 T2 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VLCDSENSE VLCD2 VLCD2 VLCD2 VLCD2 VLCD2 VLCD2 VLCD2 VLCD1 VLCD1 PAD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 x 745 745 745 745 745 745 745 745 745 745 745 745 745 745 745 745 745 745 745 745 745 745 745 745 745 745 745 745 745 745 745 745 745 745 745 745 745 745 745 745 745 745 745 745 745 y - 274 - 204 - 134 - 64 6 76 146 216 286 356 426 496 566 636 706 776 846 916 986 1196 1406 1616 1686 1756 1826 1896 1966 2036 2106 2176 2246 2316 2386 2456 2666 2736 2806 2876 2946 3016 3086 3156 3226 3296 3366 SYMBOL VLCD1 VLCD1 VLCD1 VLCD1 Dummy (VSS1) R8 R7 R6 R5 R4 R3 R2 R1 R17 C80 C79 C78 C77 C76 C75 C74 C73 C72 C71 C70 C69 C68 C67 C66 C65 C64 C63 C62 C61 C60 C59 C58 C57 C56 C55 C54 C53 C52 C51 C50 PAD 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 x
PCF2119x-2
y 3436 3506 3576 3646 3576 3506 3436 3366 3296 3226 3156 3086 3016 2946 2876 2806 2736 2666 2596 2526 2456 2386 2316 2246 2176 2106 2036 1966 1896 1756 1686 1616 1546 1476 1406 1336 1266 1196 1126 1056 986 916 846 776 706
745 745 745 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745
28. August 2000
59
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x-2
SYMBOL C49 C48 C47 C46 C45 C44 C43 C42 C41 R17DUP C40 C39 C38 C37 C36 C35 C34 C33 C32 C31 C30 C29 C28 C27 C26 C25 C24 C23 C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2
PAD 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139
x - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745
y 636 566 496 426 356 286 216 146 76 6 - 64 - 134 - 204 - 274 - 344 - 414 - 484 - 554 - 624 - 694 - 764 - 834 - 904 - 974 - 1044 - 1114 - 1184 - 1254 - 1324 - 1394 - 1464 - 1534 - 1604 - 1674 - 1744 - 1884 - 1954 - 2024 - 2094 - 2164 - 2234 - 2304 - 2374 - 2444 - 2514 - 2584 - 2654 - 2724 - 2794
SYMBOL C1 R18 R9 R10 R11 R12 R13 R14 R15 R16 Dummy (VSS1) SCL SCL T3 POR PD SDA SDA R/W RS DB0 DB1 DB2 DB3 / SA0 DB4 DB5 DB6 DB7 OSC Rec. Pat. 1 Rec. Pat. 2 Rec. Pat. 3 Rec. Pat. 4
PAD 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 169 169 170
x - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 - 745 745 745 745 745 745 745 745 745 745 745 745 745 745 745 745 745 745 745 745 745 -745 -745
y - 2864 - 2934 - 3004 - 3074 - 3144 - 3214 - 3284 - 3354 - 3424 - 3494 - 3704 - 3704 - 3634 - 3494 - 3424 - 3214 - 3004 - 2934 - 2584 - 2374 - 2164 - 1954 - 1744 - 1534 - 1324 - 1114 - 904 - 694 - 484 - 2689 2561 3681 - 3599
Table 22 Bump size PARAMETER Type Bump width Bump length Bump height Height difference in one die Convex deformation Pad size, aluminium Passivation opening CBB Wafer thickness VALUE galvanic pure Au 50 6 90 6 17.5 5 <2 <5 62 x 100 36 x 76 380 25 UNIT - m m m m m m m m
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60

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